Serialization; Latency - Motorola MPC823e Reference Manual

The PowerPC Core
At time point A the excepting instruction issues and begins executing. During the interval
between A and B, previously issued instructions are finishing execution. This interval is
equivalent to the time required for all instructions currently in progress to complete. At time
point B, the exception is recognized and during the interval between B and D the machine
state is being restored. This time is a maximum of 10 cycles. At time point C, the core starts
fetching the first instruction of the exception handler if the interrupt handler is external. It is
5 cycles if it is in the instruction cache and NO SHOW mode is on.
At time point D all state has been restored and during the interval between D and E, the
machine is saving context information in the SRR0 and SRR1 registers, disabling interrupts,
placing the machine in privileged mode, and continues the process of fetching the first
instructions of the interrupt handler from the vector table. The interval between D and E
requires a minimum of one clock. The interval between C and E depends on the memory
system and is the time it takes to fetch the first instruction of the interrupt handler. For full
history buffer restore time, it is no less then two clocks.

6.3.6 Serialization

The core has multiple execution units, each of which can be executing different instructions
at the same time. This is normally transparent to your program, but in some special
circumstances (debugging, I/O control, multiprocessor synchronization) it might become
necessary to force the machine to serialize. There are two possible serialization actions
defined for the core:
• Execution serialization—Instruction issue is halted until all instructions currently in
progress have completed execution, all internal pipeline stages and instruction buffers
have emptied, and all outstanding memory transactions are completed.
• Fetch serialization—Instruction fetch is halted until all instructions currently in the
processor have completed execution. After fetch serialization, the machine is
completely synchronized.
An attempt to issue a serializing instruction causes the machine to serialize before the
instruction issues. Only the sync instruction guarantees serialization across PowerPC
implementations. Fetching an isync instruction causes fetch serialization. Also, when the
serialize mode bit (CTRL
fetch serialization.

6.3.6.1 LATENCY

The time required to serialize the machine is also the amount of time needed to complete
the instructions currently in progress. This time is heavily dependent on the instructions in
progress and the memory system latency. It is impossible to put an absolute upper bound
on this time because the memory system design is not under the core's control. The time to
complete the current instruction is generally the machine serialization time and the specific
instruction execution time determines how long serialization takes. This can be either divide,
load, or store a multiple, string, or pair of simple load/store instructions.
6-12
) is asserted or is in debug mode, any instruction can cause
SER
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