Low-Power Operation - Motorola MPC823e Reference Manual

Clocks and Power Control
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5.5 LOW-POWER OPERATION

The low-power dividers can be used to take advantage of the MPC823e's low-power
capabilities. The low-power dividers allow you to dynamically adjust the operating
frequencies for different modules of the MPC823e and yet still maintain the SPLL lock. In
normal low mode, you can use the low-power dividers to maintain full chip functionality, but
at a much lower frequency. When you change the value of the divider, the resulting output
frequency occurs immediately. The low-power dividers are controlled in the SCCR
(described in Section 5.2.1 System Clock and Reset Control Register ) and their default
division factors are one. For example, in a 75MHz system frequency, the SYNCCLK,
LCDCLK, LCDCLK50, BRGCLK, and GCLKx are all 75MHz.
You can switch between the various low-power modes, as illustrated in Figure 5-18. Your
software must set the appropriate CSRC and LPM fields in the PLPRCR and the POW bit
in the MSR so the MPC823e can enter doze, sleep, or power-down mode from a normal
mode. The PLPRCR is described in Section 5.2.2 PLL, Low-Power, and Reset Control
Register . The MPC823e uses an interrupt to exit from any of these lower power modes. An
enabled interrupt clears the LPM field, but does not change the CSRC bit. An interrupt
switches automatically to normal high mode from normal low, doze high, doze low, sleep, or
deep-sleep mode. Interrupts are generated by:
• Wake-up interrupts (IRQx signal) from the interrupt controller.
• Real-time clock, periodic interrupt timer, timebase, or decrementer interrupts.
5-28
OPEN
LOCKED
Figure 5-17. Register Lock Mechanism
MPC823e REFERENCE MANUAL
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