Motorola MPC823e Reference Manual page 418

Memory Controller
15.5.4.2.7 Address Multiplexing. You can control the address signals that go to the
external bus. The AMA and AMB fields of the MxMR control how the address signals are
multiplexed. The SAM bit in the option register determines the address multiplexing for the
first clock cycle. The AMX field in the RAM word determines the multiplexing for subsequent
clock cycles. The lower address pins can be multiplexed between the internal upper or lower
address signals. The SAM bit outputs the upper address signals and the AMX field outputs
the lower address signals. Using the AMX field, you can output the contents of the memory
address register (MAR) on the address pins. See Table 15-6 for general configuration.
Table 15-7 shows how the AMA and AMB fields can be defined to interface with a wide
range of DRAM modules. Figure 15-31 illustrates address multiplex timing.
CLKOUT/GCLK2
GCLK1
A[0:31]
TS
Figure 15-31. Address Multiplex Timing
AMA/AMB A16 A17
000 RES RES
SIGNALS
001 RES A8
010 A6 A7
011 RES A6
100 A4 A5
101 RES A4
15-60
UPPER ADDRESS
ADDRESS CONTROLLED
BY SAM
RAM WORD 1
Table 15-7. Address Multiplexing
A18 A19 A20 A21 A22 A23
A10 A11 A12 A13 A14
A9 A10 A11 A12 A13
A8 A9 A10 A11 A12
A7 A8 A9 A10 A11
A6 A7 A8 A9 A10
A5 A6 A7 A8 A9
MPC823e REFERENCE MANUAL
LOWER ADDRESS
ADDRESS CONTROLLED
BY AMX
RAM WORD 2
PINS
A24 A25 A26 A27 A28
A15 A16 A17 A18 A19 A20
A14 A15 A16 A17 A18 A19
A13 A14 A15 A16 A17 A18
A12 A13 A14 A15 A16 A17
A11 A12 A13 A14 A15 A16
A10 A11 A12 A13 A14 A15
A29 A30 A31
A21 A22 A23
A20 A21 A22
A19 A20 A21
A18 A19 A20
A17 A18 A19
A16 A17 A18
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