Motorola MPC823e Reference Manual page 899

PM—Prescale Modulus Select
This field specifies the divide ratio of the prescale divider in the SPI clock generator. The
BRGCLK is divided by 4 * ([PM0–PM3] + 1), thus giving a clock divide ratio of 4 to 64. The
clock has a 50% duty cycle.
16.12.4.1.1 SPI Examples With Different LEN Values. The programming examples
below illustrate the effect of the LEN field and the REV bit in the SPMODE register on output
from the SPI controller. They illustrate the master mode output from the SPI controller as the
LEN varies. To help map the output process, make g through v the binary symbols, use x to
indicate a deleted bit, use __ to indicate original byte boundaries, and use _ to indicate
original nibble (4-bit) boundaries.
The initial pattern for all examples is ghij_klmn__opqr_stuv.
Example 1
LEN = 0x4
Data Selected:
Data Transmitted for REV=0:
Data Transmitted for REV=1:
Example 2
LEN = 0x7
Data Selected:
Data Transmitted for REV=0:
Data Transmitted for REV=1:
Example 3
LEN = 0xc
Data Selected:
Data Transmitted for REV=0:
Data Transmitted for REV=1:
Example 4
LEN = 0xf
Data Selected:
Data Transmitted for REV=0:
Data Transmitted for REV=1:
MOTOROLA
(Data Size = 5)
xxxj_klmn_xxxr_stuv
nmlk_j__vuts_r
j_nmlk__r_stuv
(Data Size = 8)
ghij_klmn_opqr_stuv
nmlk_jihg__vuts_rqpo
ghij_klmn__opqr_stuv
(Data Size = 13)
ghij_klmn_xxxr_stuv
nmlk_jihg__vuts_r
r_stuv__ghij_klmn
(Data Size = 16)
ghij_klmn_opqr_stuv
nmlk_jihg__vuts_rqpo
opqr_stuv__ghij_klmn
MPC823e REFERENCE MANUAL
Communication Processor Module
16-445