Instruction Cache; Features - Motorola MPC823e Reference Manual

SECTION 9

INSTRUCTION CACHE

The MPC823e instruction cache is a 16K four-way, set associative storage area. It is
organized into 256 sets, four lines per set and four words per line. Cache lines are aligned
on 4-word boundaries in memory and can be used as an SRAM that allows the application
to lock critical code segments that need fast and deterministic execution time. The cache
access cycle begins with an instruction request from the instruction unit in the core. If a
cache hit occurs, the instruction is delivered to the instruction unit and if a cache miss
occurs, the cache initiates a burst read cycle on the internal bus with the address of the
requested instruction. The first word received from the bus is considered the requested
instruction. The cache forwards this instruction to the instruction unit of the core as soon as
it is received from the internal bus. A cache line is then selected to receive the data that will
be coming from the bus. A least recently used (LRU) replacement algorithm is used to select
a line when no empty lines are available.
Instruction cache coherency in a multiprocessor environment is maintained by the software
and supported by a fast hardware invalidation capability. Figure 9-1 illustrates a block
diagram view of the cache organization and Figure 9-2 illustrates a view of the cache's data
path.

9.1 FEATURES

The following is a list of the instruction cache's main features:
• 16K Four-Way, Set-Associative at Four Words Per Line
• Implements the LRU Replacement Policy
• Parked on the Internal Bus
• Lockable Cache Lines
• "Critical word first" Burst Access
• Contains Stream Hit, which Allows Fetching from the Burst Buffer and of the Word
Currently on the Internal Bus
• Operates in Parallel with the Core to Maximize Performance
• Cache Control
Supports PowerPC
Supports load and lock (cache line granularity)
MOTOROLA
™
invalidate instruction
MPC823e REFERENCE MANUAL 9-1