Motorola MPC823e Reference Manual page 563

BPR—Bursts Per Request
This field determines how many bursts will be transferred per request.
00 = One burst per request.
01 = Two burst per request.
10 = Reserved.
11 = Four bursts per request.
• Field Base Address Register—This 32-bit register specifies the field destination base
address. FBAR is incremented by the number of bytes per line after each field. It is used
in interlaced mode only.
• Number of Fields Per Frame Register—This 16-bit register specifies the number of field
per frame. It is used in interlaced mode only. NFLD is decremented after each field.
• Lines Per Field Count Register —This 16-bit register specifies the number of lines per
field. It is used in interlaced mode only.
• Lines Per Field Register—This 16-bit register specifies the number of remaining lines
to the end of the field. It is used in interlaced mode only, and must be initialized to the
value of the LCR. L_CNT is decremented after each line.
• Bytes Per Line Register—This 16-bit register specifies the number of bytes per line. The
value must be divisible by 16 for one burst per request, by 32 for two bursts per request,
or by 64 for four bursts per request. It is used in interlaced mode only.
• Raw Bytes Register—This 16-bit register specifies the number of bytes to skip from the
end of one line to the beginning of the next line. It is used in interlaced mode only.
16.6.3.12 IDMA STATUS REGISTERS. The 8-bit IDMA 1 and 2 status registers (IDSRx)
are used to report events recognized by the IDMA controller. When an event is recognized,
the IDMA controller sets the corresponding bit in the IDSRx. These memory-mapped
registers can be read at any time. A bit is reset by writing a one (writing a zero has no effect).
IDSR1 AND IDSR2
BIT 0 1
FIELD
RESET
R/W
ADDR
Bits 0–5 and 7—Reserved
These bits are reserved and must be set to 0.
DONE—IDMA Transfer Done
This bit indicates that the IDMA channel terminated a transfer. It will be set after the byte
count in the BCR of the single-buffer mode parameter RAM has reached zero.
MOTOROLA
2 3 4
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x910 (IDSR1), 0x918 (IDSR2)
MPC823e REFERENCE MANUAL
Communication Processor Module
5 6
DONE RESERVED
0
R/W R/W
7
0
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