Table of Contents
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TABLE OF CONTENTS (Continued)
Paragraph
Number
7.1
PowerPC User Instruction Set Architecture (Book I) ............................ 7-1
7.1.1
Computation Modes ................................................................... 7-1
7.1.2
Reserved Fields ......................................................................... 7-1
7.1.3
Classes of Instructions ............................................................... 7-1
7.1.4
Exceptions .................................................................................. 7-2
7.1.5
The Branch Processor ............................................................... 7-2
7.1.6
Fetching Instructions .................................................................. 7-2
7.1.7
Branch Instructions .................................................................... 7-2
7.1.7.1
7.1.7.2
7.1.8
The Fixed-Point Processor ......................................................... 7-2
7.1.8.1
7.1.8.2
7.1.9
The Load/Store Processor ......................................................... 7-3
7.1.9.1
7.1.9.2
7.1.9.3
7.1.9.4
7.1.9.5
7.1.9.6
7.2
PowerPC Virtual Environment Architecture (Book II) ............................ 7-4
7.2.1
Storage Model ............................................................................ 7-4
7.2.1.1
7.2.1.2
7.2.2
The Effect Of Operand Placement on Performance .................. 7-5
7.2.3
The Storage Control Instructions ............................................... 7-5
7.2.4
Timebase ................................................................................... 7-6
7.3
PowerPC Operating Environment Architecture (Book III) ..................... 7-6
7.3.1
The Branch Processor ............................................................... 7-6
7.3.1.1
7.3.1.2
7.3.1.3
7.3.2
The Fixed-Point Processor ......................................................... 7-6
7.3.2.1
7.3.2.2
7.3.3
Storage Model ............................................................................ 7-6
7.3.3.1
7.3.4
Reference and Change Bits ....................................................... 7-7
7.3.5
Storage Protection ..................................................................... 7-7
7.3.6
Storage Control Instructions ....................................................... 7-7
iv
Title
Invalid Branch Instruction Forms .................................... 7-2
Branch Prediction ........................................................... 7-2
Move To/From System Register Instructions ................. 7-3
Fixed-Point Arithmetic Instructions ................................. 7-3
With Update Instructions ................................................ 7-3
Fixed-Point Load and Store Multiple Instructions ........... 7-3
Fixed-Point Load String Instructions ............................... 7-3
Storage Synchronization Instructions ............................. 7-4
Optional Instructions ....................................................... 7-4
Little-Endian Byte Ordering ............................................ 7-4
Memory Coherence ........................................................ 7-4
Atomic Update Primitives ............................................... 7-4
Machine State Register .................................................. 7-6
Processor Version Register ............................................ 7-6
Branch Processors Instructions ...................................... 7-6
Unsupported Registers ................................................... 7-6
Added Registers ............................................................. 7-6
Address Translation ........................................................ 7-6
MPC823e REFERENCE MANUAL
Page
Number
MOTOROLA
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