Motorola MPC823e Reference Manual page 560

Communication Processor Module
Interlaced mode can be set up using the following steps:
1. Initialize the IDMA single buffer mode parameter RAM.
2. In the RCCR, set the EIE bit to 1 and the DR1M bit according to the requested mode.
See Section 16.2.5 RISC Configuration and Control Registers for more
information.
3. If edge-sensitive mode is selected, program the EDM15 bit of the PCINT register to
the requested mode (falling edge/any edge).
4. In the PCSO register, set the DREQ1 bit to 1. See Section 16.14.9.4 Port C Special
Options Register for more information.
When configured to single buffer mode, the IDMA parameter RAM is overlayed with the
specific parameters in Table 16-22.
Table 16-22. Single-Buffer Mode Parameter RAM Map
ADDRESS NAME
DMA Base + 00 BAPR*
DMA Base + 04 BCR*
DMA Base + 08 DCMR*
DMA Base + 0C FBAR*
DMA Base + 10
DMA Base + 12 NFLD*
DMA Base + 14
DMA Base + 16 L_CNT*
DMA Base + 18 BPLR
DMA Base + 1A RBR
DMA Base + 1C to
DMA Base + 3F
NOTE: You are only responsible for initializing the items in bold.
* Modified by the IDMA controller during operation and must be reinitialized before starting a
new IDMA transaction.
DMA base = (IMMR & 0xFFFF0000) + 0x3CC0 (IDMA1).
All references to registers in the parameter RAM table are actually implemented in the dual-port RAM area as
a memory-based register.
16-106
DESTINATION ADDRESS GENERATION MODE
WIDTH
PROGRESSIVE
Word Buffer Address Pointer
Word Byte Count Register
Word DMA Channel Mode Register
Word Not Assigned
RES Half-Word
Half-Word Not Assigned
LCR Half-Word Not Assigned
Half-Word Not Assigned
Half-Word Not Assigned
Half-Word Not Assigned
RES Word
MPC823e REFERENCEMANUAL
INTERLACED
Current Buffer Address Pointer
Current Bytes Per Line
DMA Channel Mode Register
Field Base Address Register
Reserved
Number of Fields Register
Lines Per Field Count Register
Current Line Count
Bytes Per Line Register
Raw Bytes Register
Reserved
Reserved
Reserved
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