Motorola MPC823e Reference Manual page 604

Communication Processor Module
11. SISTR and SIRP do not need to be read, but can be used for debugging information
once the channels are enabled.
12. Enable SCC2 to HDLC operation (to handle the LAPD protocol of the D channel). Set
SCC2 and SMC1 to transparent operation.
16.7.7 GCI Interface Operation
The normal mode of the general circuit interface (GCI) and SCIT are fully supported by the
MPC823e. It also supports the D channel access control in S/T interface terminals by using
the command/indication (C/I) channel for that function.
The GCI bus consists of four lines—two data lines, a clock, and a frame synchronization line.
Usually, an 8kHz frame structure defines the various channels within the 256kbps data rate.
The MPC823e supports an independent GCI bus and has independent receive and transmit
sections. The interface can also be used in a multiplexed frame structure on which up to
eight physical layer devices can multiplex their GCI channels. In this mode, the data rate
would be 2,048kbps. In the GCI bus, the clock rate is twice the data rate. The serial interface
divides the input clock by two to produce the data clock. The MPC823e also has data strobe
lines that are used as an interface for devices that do not support the GCI bus. The GCI
signals for each transmit and receive channel are as follows:
• L1RSYNC x —Used as a GCI sync signal. Input to the MPC823e. This signal indicates
that the clock periods following the pulse designate the GCI frame.
• L1RCLK x —Used as a GCI clock. Input to the MPC823e. The L1RCLK x signal is twice
the data clock.
• L1RXD x —Used as a GCI receive data. Input to the MPC823e.
• L1TXD x —Used as a GCI transmit data. Open-drain output. Valid only for the bits that
are supported by the IDL. Otherwise, it is three-stated.
L1xCLK
(2X THE DATA RATE)
L1xSYNC
L1RXDx
B1
L1TXDx
B1
16-150
B2
B2
Figure 16-61. GCI Bus Signals
MPC823e REFERENCE MANUAL
(CLOCK IS NOT TO SCA
MONITOR D1 D2 C/ I
MONITOR D1 D2 C/ I
T E
T E
MOTOROLA