Level One Descriptor - Motorola MPC823e Reference Manual

11.5.1 Level One Descriptor

The following table describes the hardware-assisted level one descriptor format that
minimizes the software tablewalk routine.
LEVEL ONE DESCRIPTOR FORMAT
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD L2BA
RESET —
R/W R/W
ADDR
NOTE: — = Undefined. The default values depend on the state of system memory.
L2BA—Level 2 Table Base Address
This field contains a pointer to a base address of the level 2 table. Bits 18 and 19 are only
used when MD_CTR
TWAM
Bits 20–22—Reserved
These bits are reserved and must be set to 0.
APG—Access Protection Group
This field contains access protection for the entire memory segment associated with this
entry of the table.
G—Guarded Storage Attribute for Entry
0 = Unguarded storage.
1 = Guarded storage.
PS—Page Size Level One
00 = Small (4K or 16K).
01 = 512K.
11 = 8M.
10 = Reserved.
WT—Writethrough Attribute for Entry
0 = Copyback cache policy region (default).
1 = Writethrough cache policy region.
MOTOROLA
3 4 5 6 7
L2BA
—
R/W
SYSTEM MEMORY XXXXX0000
19 20 21 22 23
RESERVED
—
R/W
SYSTEM MEMORY XXXXX002
= 1. Otherwise, they must be set to 0.
MPC823e REFERENCE MANUAL
Memory Management Unit
8 9 10 11 12
24 25 26 27 28
APG G PS
— — —
R/W R/W R/W
13 14 15
29 30 31
WT V
— —
R/W R/W
11-9