Motorola MPC823e Reference Manual page 644

Communication Processor Module
If the CTSx pin is not already asserted when the RTSx pin is asserted, then the delays to
the first bit of data depend on when CTSx is asserted. Figure 16-67 illustrates that the delay
between CTSx and the data can be approximately 0.5- to 1-bit time or 0-bit times, depending
on how the CTSS bit is set in the GSMR_H.
TCLK
TXDx
(OUTPUT)
RTSx
(OUTPUT)
CTSx
(INPUT)
TCLK
TXDx
(OUTPUT)
RTSx
(OUTPUT)
CTSx
(INPUT)
Figure 16-67. CTSx Output Delays Asserted for Synchronous Protocols
16-190
FIRST BIT OF FRAME DATA
CTS SAMPLED LOW HERE
NOTE: CTSS is set to 0 in the GSMR. CTSP is a "don't care".
FIRST BIT OF FRAME DATA
NOTE: CTSS is set to 1 in the GSMR. CTSP is a "don't care".
MPC823e REFERENCE MANUAL
LAST BIT OF FRAME DATA
LAST BIT OF FRAME DATA
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