Table of Contents
Advertisement
Memory Controller
Refer to Section 15.5.4.2 RAM Word Operation for more specific DRAM example
information.
00 = 1-cycle disable period.
01 = 2-cycle disable period.
10 = 3-cycle disable period.
11 = 4-cycle disable period.
G0CLB—General Line 0 Control B
This field selects the address line that is output to the internal GPL0 signal when the UPMB
is selected to control memory access. It can be used for precharge control on SDRAMs.
000 = A12 is selected.
001 = A11 is selected.
010 = A10 is selected.
011 = A9 is selected.
100 = A8 is selected.
101 = A7 is selected.
110 = A6 is selected.
111 = A5 is selected.
GPLB4DIS—GPLB4 Output Line Disable
This bit determines whether or not the UPWAITB/GPL_B4 pin will behave as an output line
controlled by the internal GPL4 signal and the UPM RAM word.
0 = UPWAITB/GPL_B4 is defined as GPL_B4.
1 = UPWAITB/GPL_B4 is defined as UPWAITB.
RLFB—Read Loop Field B
This field specifies the number of times a loop defined in the UPMB RAM word is executed
for a burst read or single beat read cycle.
0001 = The loop is executed 1 time.
0010 = The loop is executed 2 times.
0011 = The loop is executed 3 times.
0100 = The loop is executed 4 times.
0101 = The loop is executed 5 times.
0110 = The loop is executed 6 times.
0111 = The loop is executed 7 times.
1000 = The loop is executed 8 times.
1001 = The loop is executed 9 times.
1010 = The loop is executed 10 times.
1011 = The loop is executed 11 times.
1100 = The loop is executed 12 times.
1101 = The loop is executed 13 times.
1110 = The loop is executed 14 times.
1111 = The loop is executed 15 times.
0000 = The loop is executed 16 times.
15-24
MPC823e REFERENCE MANUAL
MOTOROLA
Advertisement
Table of Contents
