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Introduction
1.2.1 The Embedded PowerPC Core
The PowerPC core complies with standard PowerPC architecture. It has a fully static design
that consists of three functional blocks—the integer block, hardware multiplier/divider, and
load/store block. The core supports integer operations on a 32-bit internal data path and
32-bit arithmetic hardware. Its interface to the internal and external buses is 32 bits. The
core uses a two-instruction load/store queue, four-instruction prefetch queue, and a
six-instruction history buffer. It performs branch folding and branch prediction with
conditional prefetch, but without conditional execution. With single bus cycles, the core can
operate on 32-bit external operands and with critical-word-first in multiple bus cycles. The
PowerPC integer block supports 32 x 32-bit fixed-point general-purpose registers and can
execute one integer instruction per clock cycle.
The PowerPC core is integrated with the memory management units, an instruction cache,
and a data cache. The memory management units (MMUs) provide 32-entry,
fully-associative instruction and data TLBs, with multiple page sizes of 4K (1K protection),
16K, 512K, and 8M. They support 16 virtual address spaces and 16 protection groups.
Special registers are available to support software tablewalk and update.
The instruction cache is 16K, four-way, set-associative with physical addressing. It allows
single-cycle accesses on hit with no added latency for miss. It is four words per line and
supports burst line fill using an LRU replacement algorithm. The cache can be locked on a
line basis for application critical routines. The data cache is 8K, four-way, set-associative
with physical addressing. It allows single-cycle accesses on hit with one added clock latency
for miss. It has four words per line and supports burst line fill using an LRU replacement
algorithm. The cache can be locked on a line basis for application critical data and can be
programmed to support copyback or writethrough mode via the memory management unit.
The cache-inhibit mode can be programmed per MMU page. The PowerPC core, with its
instruction and data caches, can deliver approximately 99MIPS at 75MHz (using Dhrystone
2.1) or 172K Dhrystones, based on the assumption that it is issuing one instruction per cycle
with a cache hit rate of 94%.
1.2.2 The System Interface Unit
The system interface unit supports traditional 68K big-endian memory systems, traditional
x86 little-endian memory systems, and PowerPC little-endian memory systems. It also
provides power management functions, reset control, a PowerPC decrementer, PowerPC
timebase, and real-time clock. Although the PowerPC core is a 32-bit device internally, it can
be configured to operate with an 8-, 16-, or 32-bit data bus. Regardless of the system bus
size, dynamic bus sizing is supported, which allows 8-, 16-, and 32-bit peripherals and
memory to coexist on a 32-bit system bus.
The memory controller supports up to eight memory banks with glueless interfaces to
DRAM, SRAM, EPROM, Flash EPROM, SDRAM, EDO and other peripherals with two-clock
initial access to external SRAM and bursting support. It provides variable block sizes
between 32K and 256M. The memory controller has 0 to 20 wait states for each bank of
memory and can use address type matching to qualify each memory bank access. It
provides four byte-enable signals for varying width devices, one output-enable signal, and
one boot chip-select that is available at reset.
1-8
MPC823e REFERENCE MANUAL
MOTOROLA
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