Motorola MPC823e Reference Manual page 374

Memory Controller
PER6—Parity Error Bank 6
When this bit is set it indicates that a parity error was detected during a Bank 6 read cycle
initiated by the memory controller.
PER7—Parity Error Bank 7
When this bit is set it indicates that a parity error was detected during a Bank 7 read cycle
initiated by the memory controller.
WPER—Write-Protection Error
This bit is set when a write-protect error has occurred on a write cycle to a write-protected
bank. The write-protect error is also stored in the transfer error status register of the system
interface unit. See Section 12.12.1.4 Transfer Error Status Register for more information.
If the bus monitor is enabled, then TEA is asserted. The TEA signal will generate a machine
check exception if it occurs between a TS and TA signal. When a TA is asserted before a
write-protection error is detected, the TEA that occurs will not generate a machine check
exception. Refer to Section 12.4 The Bus Monitor for more information.
Note: If the bus monitor is disabled and the write-protect error occurs, TEA assertion
will not occur. See Section 12.12.1.4 Transfer Error Status Register for more
information.
Bits 9–15—Reserved
These bits are reserved and must be set to 0.
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