Motorola MPC823e Reference Manual page 757

Communication Processor Module
In both cases, an interrupt is issued according to the I bit in the RX or TX buffer descriptor.
By appropriately setting the I bit in each buffer descriptor, interrupts are generated after each
buffer or group of buffers is transmitted. The serial communication controllers then proceed
to the next buffer descriptor in the table and any whole number of bytes can be transmitted.
If the REVD bit in the GSMR_H is set, each data byte is reversed in its bit order before being
transmitted and the most-significant bit of each octet is transmitted first.
You can decrease the latency of the transmitter by decreasing the transmit FIFO size. This
option is enabled by the TFL bit in the GSMR_H and causes transmitter underruns at higher
transmission speeds. An optional CRC can be appended to each transparent frame if it is
enabled in the TX buffer descriptor. The CRC pattern is chosen in the TCRC field of the
GSMR_H.
16.9.21.3 SCCx TRANSPARENT CHANNEL FRAME RECEPTION PROCESS. When
the core enables the SCCx receiver in transparent mode, it waits to achieve synchronization
before data is received. The receiver can be synchronized to the data by a synchronization
pulse or Sync pattern.
After a buffer is filled, the serial communication controllers clear the E bit in the RX buffer
descriptor and generate an interrupt if the I bit is set. They then moves to the next RX buffer
descriptor in the table and begin moving data to its associated buffer. If the next buffer is not
available, the BSY bit in the SCCE–Transparent register signifies a busy signal that can
generate a maskable interrupt. The receiver reverts to hunt mode when the ENTER HUNT
MODE command or an error is received. If the REVD bit in the GSMR_H is set, each data
byte is reversed in its bit order before it is written to memory.
You can decrease the latency of the receiver by decreasing the receive FIFO width. This
option is enabled by the RFW bit in the GSMR_H and causes receiver overruns at higher
transmission speeds. The receiver always checks the CRC of the received frame, according
to the TCRC field in the GSMR_H. If a CRC is not required, the resulting errors can be
ignored.
16.9.21.4 ACHIEVING SYNCHRONIZATION IN TRANSPARENT MODE. Once the
SCCx transmitter is enabled for transparent operation in the GSMR_H, the TX buffer
descriptor is prepared and the transmit FIFO is preloaded by the SDMA channel, another
process must occur before data can be transmitted. It is called transmit synchronization.
Once the SCCx receiver is enabled for transparent operation in the GSMR_H and the RX
buffer descriptor is emptied for a serial communication controller, another process (called
receive synchronization ) must occur before data can be received. You can have bit-level
control of the synchronization process when receiving and transmitting by using either an
inline synchronization pattern or external synchronization signals.
MOTOROLA MPC823e REFERENCE MANUAL 16-303