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20. Write 0x001A to the SCCM–HDLC to enable the TXE, RXF, and TXB interrupts.
21. Write 0x20000000 to the CIMR to allow the SCC2 to generate a system interrupt. The
CICR must also be initialized.
22. Write 0x00000000 to the MODE field of the GSMR_H to enable normal behavior of the
CTS and CD pins and idles between frames (as opposed to flags).
23. Write 0x00028800 to the MODE field of the GSMR_L to configure the CTS and CD
pins to automatically control transmission, reception (DIAG field), and HDLC mode.
Normal operation of the transmit clock is selected and the TCI bit is cleared. The
TDCR and the RDCR must be configured to 16x clock mode and the receiver decoding
method must be NRZI. Notice that the transmitter (ENT) and receiver (ENR) have not
been enabled. If you want inverted infra-red operation, set the RINV and TINV bits in
the GSMR_L.
24. Set the PSMR–HDLC to 0x1000 to configure two opening and one closing flag, 16-bit
CCITT-CRC, and prevention of multiple frames in the FIFO.
25. Write 0x0108 for a 1.152Mb/s infrared rate or 0x0084 for a 0.576Mb/s infrared rate to
the IRSIP register. When working with Timer 2 as the SIP trigger, the values must be
0x2108 for a 1.153Mb/s infrared or 0x2084 for a 0.572Mb/s.
26. Write 0x0003 to the IRMODE register to enable the infrared and to set the mode of
operation to middle-speed.
27. Program the TMR2 register when working with Timer 2 as the SIP trigger.
28. Write 0x00028830 to GSMR_L to enable the SCC2 transmitter and receiver. This
additional write ensures that the ENT and ENR bits will be enabled last.
Note: After 5 bytes and CRC have been transmitted, the TX buffer descriptor is
automatically closed. Once a complete frame is received, the RX buffer
descriptor is closed. Any data received after 256 bytes or a single frame causes
a busy (out-of-buffers) condition since only one RX buffer descriptor is prepared.
MOTOROLA
MPC823e REFERENCE MANUAL
Communication Processor Module
16-299
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