Motorola MPC823e Reference Manual page 562

Communication Processor Module
BO—Byte Ordering
You must set this field to select the required byte ordering of the data buffer. If this field
is modified on-the-fly, it will take effect at the beginning of the next buffer descriptor.
00 = DEC/Intel convention is used for byte ordering (swapped operation). It is also
called little-endian byte ordering. The transmission order of bytes within a buffer
word is reversed as compared to the Motorola mode. This mode is supported only
for 32-bit port size memory.
01 = PowerPC little-endian byte ordering. As data is transmitted onto the serial line
from the data buffer, the least significant byte of the buffer double-word contains
data to be transmitted earlier than the most significant byte of the same buffer
double word.
1X = Motorola byte ordering (normal operation). It is also called big-endian byte
ordering. As data is transmitted onto the serial line from the data buffer, the most
significant byte of the buffer word contains data to be transmitted earlier than the
least significant byte of the same buffer word.
AT—Address Type 1–3
This field contains the function code value used during this SDMA channel memory
access. AT0 will be driven with a one to identify this SDMA channel access as a
DMA-type access.
STR—Start
This bit enables the IDMA channel. You must set it after you program BAPR and BCR.
It is cleared by the channel upon completion of the transfer and the byte count in BCR
is exhausted.
0 = DMA channel is disabled.
1 = DMA channel is enabled.
EDGE—Edge-Sensitive DREQ1
This bit controls whether the communication processor module will be interlocked to
the external SDACK1 signal before exiting the IDMA routine. This bit must be cleared
if level-sensitive DREQ1 is used. If the DR1M bit of the RCCR is set to 1, this bit must
be set to 0.
0 = Level-sensitive mode. The communication processor module will wait until
SDACK1 is seen externally before executing the IDMA routine.
1 = Edge-sensitive mode. The communication processor module may exit the IDMA
routine before SDACK1 is seen externally.
ITLC—Interlaced Mode
This bit controls the destination address bit generation.
0 = Progressive (non-interlaced) address generation.
1 = Interlaced address generation.
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