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14.2 BIG-ENDIAN SYSTEM FEATURES
The following is a list of the big-endian system's main features:
• Caches, U-Bus, E-Bus, System Memory, and I/O Organization Format is Big-Endian
• Same Byte Order between the Media and System Memory
• Communication Processor Module Writes and Reads Big-Endian U-Bus Data
• PCI Bridge Operates in Big-Endian Mode as Needed
14.3 POWERPC LITTLE-ENDIAN SYSTEM FEATURES
The following is a list of the PowerPC little-endian system's main features:
• Caches, U-Bus, E-Bus, System Memory, and E-Bus Attached I/O Organization Format
is Big-Endian
• PCI Bus Format is Little-Endian
• Data Access Constraints that Follow the PowerPC Little-Endian Rules
• Address Munging in the Core and Communication Processor Module Follows the
Guidelines in Table 14-1
• The PCI Bridge Operates in Little-Endian Mode as Needed. Swap and Address
Demunging is Performed by the PCI Bridge on the PCI I/O to the System Memory Path.
• The Stream Hit Mechanisms of the Instruction and Data Caches Operate Less
Efficiently when Address Munging is Performed on Cache Accesses. Some
Performance Degradation is Expected when Working in this Mode.
14.4 SETTING THE ENDIAN MODE OF OPERATION
The endian mode must be set early in the reset routine and remain unchanged for the
duration of system operation. The MPC823e core is in big-endian mode after reset. To
switch between the different endian modes of operation, the core must run in serialized
mode and the caches must be disabled. It is not recommended that you switch back and
forth between modes. To transfer the system to little-endian mode, the DC_CSR
be set by writing 0b0101 to the CMD field of the DC_CSR with an mtspr instruction on an
even word boundary (A29=0). Further instructions must be little-endian. However, there are
some idiosyncrasies with little-endian mode itself.
To transfer the system to the PowerPC little-endian mode, the MSR
be changed with an mtmsr instruction on an odd word boundary (A29=1). The instruction
that is executed next will be fetched from this address plus 8. If the instruction resides on an
even word boundary (A29=0), then this instruction will be executed twice because of
address munging. The instruction to transfer the system back to the big-endian mode must
reside on an even word boundary (A29=0). The next instruction will be fetched from this
address plus 12. The BO field of the function code registers (FCRs) in the communication
processor module must be set to the required endian format for the buffer descriptor.
MOTOROLA
MPC823e REFERENCE MANUAL
Endian Modes
bit must
LES
and MSR
bits must
LE
ILE
14-5
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