Motorola MPC823e Reference Manual page 444

Memory Controller
You can significantly increase the performance of a page read access when you set
GPLA4DIS to 1 in the MAMR and ignore the GPL_A4 pin. The processor samples the data
bus at the falling edge of GCLK1 when the TA signal is asserted. Figure 15-50 illustrates
how to modify the burst read access to page mode DRAM (no loop) using this feature.
During the four consecutive data beats, the TA signal in the figure is asserted to ensure a
data transfer on every data clock. The figure also illustrates how the nine cycles of the burst
read access shown in Figure 15-43 can be reduced to 6 clock cycles (for 32-bit port size
memory). You can reduce the cycles by using faster DRAM or a slower system clock that
meets the DRAM access time. When a 16-bit port size memory is connected, the reduction
is from 17 to 10 cycles and when an 8-bit port size memory is connected, the reduction is
from 33 to 18 cycles.
15-86 MPC823e REFERENCE MANUAL MOTOROLA