Motorola MPC823e Reference Manual page 226

Memory Management Unit
During the memory management unit's address translation, the most-significant bits of the
missed effective address are replaced by the real page address bits from the level two page
descriptor. The number of replaced bits depends on the page size. The rest of the real
address bits are taken directly from the effective address. See Table 11-1 for details.
Table 11-1. Number of Effective Address Bits Replaced
Table 11-2. Number of Identical Entries Required in
PAGE SIZE
1K
4K
16K
512K
8M
Table 11-3. Number of Identical Entries Required in
PAGE SIZE
1K
4K
16K
512K
8M
11-8
By Real Address Bits
PAGE SIZE NUMBER OF REPLACED
EFFECTIVE ADDRESS BITS
1K
4K
16K
512K
8M
the Level One Table
MD_CTR
TWAM
1
1
1
1
8
the Level Two Table
MD_CTR
TWAM
1
4
16
512
1,024
MPC823e REFERENCE MANUAL
20
20
18
13
9
= 0 MD_CTR
TWAM
—
1
1
1
2
= 0 MD_CTR
TWAM
—
1
4
128
1,024
= 1
= 1
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