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11.6.1.13 MMU TABLEWALK SPECIAL REGISTER. The MMU tablewalk special
(M_TW) register is used as a scratch register in the software tablewalk interrupt handler.
M_TW
BIT
0
1
2
RESET
R/W
ADDR
BIT
16
17
18
RESET
R/W
ADDR
NOTE: — = Undefined.
11.6.2 MMU Data Content-Addressable Registers
The MD_CAM, MD_RAM0, and MD_RAM1 registers are interface registers that allow you
to read the data memory management unit CAM and RAM entries. If you try to write to the
MD_CAM register using the mtspr instruction, the CAM and RAM values of the entry
indexed by the DTLB_INDX field to MD_CAM, MD_RAM0, and MD_RAM1 will be loaded.
The source register in the mtspr instruction can be any register, since its value is not used.
The values of the MD_CAM, MD_RAM0, and MD_RAM1 registers can be read using the
mfspr instruction. If you try to write to the MD_RAM0 and MD_RAM1 registers using the
mtspr instruction, it will be considered a NOP (no operation) instruction.
MOTOROLA
3
4
5
6
7
M_TW
R/W
SPR 799
19
20
21
22
23
M_TW
R/W
SPR 799
MPC823e REFERENCE MANUAL
Memory Management Unit
8
9
10
11
12
24
25
26
27
28
13
14
15
29
30
31
11-37
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