Motorola MPC823e Reference Manual page 657

• Even, odd, force, or no parity generation
• Even, odd, force, or no parity check
• Frame error, noise error, break, and idle detection
• Transmit preamble and break sequences
• Freeze transmission option with low-latency stop
16.9.15.2 NORMAL ASYNCHRONOUS MODE. In normal asynchronous mode, the
receive shift register receives the incoming data on the RXDx pin. The control bits in the
PSMR–SCC UART register define the length and format of the UART character and each
bit is received in the following order:
1. Start bit
2. 5–8 data bits (LSB first)
3. Address/data bit (optional)
4. Parity bit (optional)
5. Stop bits
The receiver uses a clock 8x, 16x, or 32x faster than the baud rate and samples each bit of
the incoming data three times around its center. The value of the bit is determined by the
majority of those samples and if they do not all agree, a noise indication counter is
incremented. When a complete byte has been clocked in, the contents of the shift register
are transferred to a UART receive data buffer. If there is an error in this character, the
appropriate error bits are set by the communication processor module.
The SCCx UART controller can receive fractional stop bits. The next character's start bit can
begin any time after the three middle samples are taken. The UART transmit shift register
transmits the outgoing data on the TXDx pin. Data is then synchronously clocked with the
transmit clock, which may have either an internal or external source. The bit transmission
order is LSB first, but only the data portion of the UART frame is actually stored in the data
buffers. The start and stop bits are always generated and stripped by the SCCx UART
controller. The parity bit can also be generated in transmission and checked during
reception and although it is not stored in the data buffer, its value can be inferred from the
reporting mechanism of the data buffer. Similarly, the optional address bit is not stored in
the transmit or receive data buffer, but is implied from the buffer descriptor itself. Parity is
generated and checked for the address bit. The RFW bit of the GSMR_H must be set for an
8-bit receive FIFO.
16.9.15.3 SYNCHRONOUS MODE. In synchronous mode, the SCCx UART controller
uses a 1x data clock for timing. The receive shift register receives the incoming data on the
RXDx pin synchronously to the clock. The length and format of the serial word in bits are
defined by the control bits in the PSMR–SCC UART register in the same way they are
defined in asynchronous mode. When a complete byte has been clocked in, the contents of
the shift register are transferred to a UART receive data buffer. If there is an error in this
character, then the appropriate error bits are set by the communication processor module.
MOTOROLA MPC823e REFERENCE MANUAL
Communication Processor Module
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