Motorola MPC823e Reference Manual page 78

Microprocessor for mobile computing
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Memory Map
Table 3-1. MPC823e Internal Memory Map (Continued)
INTERNAL
ADDRESS
09C
POR3—PCMCIA Interface Option Register 3
0A0
PBR4—PCMCIA Interface Base Register 4
0A4
POR4—PCMCIA Interface Option Register 4
0A8
PBR5—PCMCIA Interface Base Register 5
0AC
POR5—PCMCIA Interface Option Register 5
0B0
PBR6—PCMCIA Interface Base Register 6
0B4
POR6—PCMCIA Interface Option Register 6
0B8
PBR7—PCMCIA Interface Base Register 7
0BC
POR7—PCMCIA Interface Option Register 7
0C0 to 0E3
RES—Reserved
0E4
PGCRB—PCMCIA Interface General Control Register B
0E8
PSCR—PCMCIA Interface Status Change Register
0EC to 0EF
RES—Reserved
0F0
PIPR—PCMCIA Interface Input Pins Register
0F4 to 0F7
RES—Reserved
0F8
PER—PCMCIA Interface Enable Register
0FC to 0FF
RES—Reserved
MEMORY CONTROLLER
100
BR0—Base Register Bank 0
104
OR0—Option Register Bank 0
108
BR1—Base Register Bank 1
10c
OR1—Option Register Bank 1
110
BR2—Base Register Bank 2
114
OR2—Option Register Bank 2
118
BR3—Base Register Bank 3
11C
OR3—Option Register Bank 3
120
BR4—Base Register Bank 4
124
OR4—Option Register Bank 4
128
BR5—Base Register Bank 5
12C
OR5—Option Register Bank 5
130
BR6—Base Register Bank 6
134
OR6—Option Register Bank 6
3-2
REGISTER
MPC823e REFERENCE MANUAL
SIZE
PAGE NUMBER
(IN BITS)
LOCATION
32
17-17
32
17-16
32
17-17
32
17-16
32
17-17
32
17-16
32
17-17
32
17-16
32
17-17
32
17-15
32
17-11
32
17-9
32
17-13
32
15-9
32
15-11
32
15-9
32
15-11
32
15-9
32
15-11
32
15-9
32
15-11
32
15-9
32
15-11
32
15-9
32
15-11
32
15-9
32
15-11
MOTOROLA

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