Motorola MPC823e Reference Manual page 445

CLKOUT/GCLK2
GCLK1
A[6:31]
ROW COL 1
TS
RD/
WR
D[0:31]
TA
CS1
( )
RAS
[0:3]
BS_A
( [0:3])
CAS
cst4 Bit 0 0 0
cst1 Bit 1 0 0
cst2 Bit 2 0 0
cst3 Bit 3 0 0
bst4 Bit 4 1 1
bst1 Bit 5 1 0
bst2 Bit 6 1 0
bst3 Bit 7 1 0
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t4 Bit 12
g1t3 Bit 13
g2t4 Bit 14
g2t3 Bit 15
g3t4 Bit 16
g3t3 Bit 17
dlt3 Bit 18 1 1
g4t3 Bit 19 0 0
g5t4 Bit 20
g5t3 Bit 21
- Bit 22
- Bit 23
loop Bit 24 0 0
exen Bit 25 0 0
amx0 Bit 26 0 0
amx1 Bit 27 0 0
na Bit 28 0 1
uta Bit 29 1 0
todt Bit 30 0 0
last Bit 31 0 0
RBS
Figure 15-50. Optimized DRAM Burst Read Access
MOTOROLA
COL 2 COL 3 COL 4
D1 D2 D3 D4
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
0 0 0
0 0 0
0 0 0
1 1 1
0 0 0
0 0 0
0 0 0
0 0 1
0 0 0
1 1 0
1 0 0
0 0 0
0 0 0
RBS+1 RBS+2 RBS+3 RBS+4
MPC823e REFERENCE MANUAL
Memory Controller
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
1
1
1
RBS+5
15-87