Motorola MPC823e Reference Manual page 182

Table 8-1. Instruction Execution Timing (Continued)
INSTRUCTIONS
Storage Control Instructions:
isync
Order Storage Access:
eieio
Cache Control:
icbi
NOTES: 1. Refer to Table 6-11 for details.
2. Refer to Section 6.4.1 Control Registers .
3. See Table 6-10 for details.
4.
DivisionLatency
Where:
5. DivisionBlockage
6. Blocking the multiply instruction is dependent on the subsequent instruction. For any subsequent
multiply instruction, the blockage is 1 clock and for any subsequent divide it is 2 clocks.
7. Assuming nonspeculative aligned access, on-chip memory, and available bus. For details, refer to
Section 6.6.5 Issuing Nonspeculative Load Instructions , Section 6.6.6 Executing Unaligned
Instructions , and Section 6.6.9 Instruction Timing .
8. Although a store (as well as mtspr for special registers external to the core) issued to the load/store
unit buffer frees the core pipeline, the next load or store will not actually be performed on the bus until
the bus is free.
MOTOROLA
LATENCY BLOCKAGE
Serialize
1
1
 34 divisorLength
–
⇒
NoOverflow 3 +
------------------------------------------------------

=
----------------------------------------------------------------------------------------------------------------------- -
⇒
Overflow
  or MaxNegativeNumber 
x
Overflow =
-- -   -------------------------------------------------------------- -

0 1 –
= DivisionLatency
MPC823e REFERENCE MANUAL
Instruction Execution Timing
EXECUTION
UNIT
Serialize Branch
1 LDST Next Load or Store
Relative to All Prior
1 LDST,
I-Cache


4
2


SERIALIZING
INSTRUCTION
Yes
is Synchronized
Load or Store
No
8-3