Mmu Instruction Ram Entry Read Register 0 - Motorola MPC823e Reference Manual

11.6.3.2 MMU INSTRUCTION RAM ENTRY READ REGISTER 0. The MMU instruction
RAM entry read register 0 (MI_RAM0) contains the physical page number and page
attributes of an entry indexed by the ITLB_INDX field of the MI_CTR. This register is only
updated when you write to the MI_CAM register.
MI_RAM0
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD RPN
RESET —
R/W R
ADDR
NOTE: — = Undefined.
RPN—Real Page Number
These bits are the most-significant bits of the page's physical address.
PS_B—Page Size
000 = 4K.
001 = 16K.
011 = 512K.
111 = 8M.
010 = Reserved.
100 = Reserved.
101 = Reserved.
110 = Reserved.
CI—Cache-Inhibit
When this bit is 0, it is not cache-inhibited.
APG—Access Protection Group
A maximum of 16 protection groups are supported and represented in one's compliment
format.
MOTOROLA
3 4 5 6 7
RPN
—
R
SPR 817
19 20 21 22 23
PS_B CI
— —
R R
SPR 817
MPC823e REFERENCE MANUAL
Memory Management Unit
8 9 10 11 12
24 25 26 27 28
APG
—
R
13 14 15
29 30 31
SFP
—
R
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