Mmu Data Ram Entry Read Register 1 - Motorola MPC823e Reference Manual

11.6.2.3 MMU DATA RAM ENTRY READ REGISTER 1. The MMU data RAM entry read
register 1 (MD_RAM1) contains the protection mode information of the entry indexed by the
DTLB_INDX field of the MD_CTR. This register is only updated when you write a value to it.
MD_RAM1
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD
RES C EVF
RESET
0 — —
R/W
R R R
ADDR
NOTE: — = Undefined.
Bits 0–16—Reserved
These bits are reserved and must be set to 0.
C—Change Bit for Data Entry TLB
0 = Unchanged region. Write access to this page results in the implementation-specific
instruction MMU interrupt invocation. Software must take an appropriate action
before setting this bit to 1.
1 = Changed region. Write access is allowed to this page.
EVF—Entry Valid Flag
0 = Entry is invalid.
1 = Entry is valid.
MOTOROLA
3 4 5 6 7
RESERVED
0
R
SPR 826
19 20 21 22 23
SA SAT URP0
— —
R R
SPR 826
MPC823e REFERENCE MANUAL
Memory Management Unit
8 9 10 11 12
24 25 26 27 28
UWP0 URP1 UWP1 URP2 UWP2
— — — — —
R R R R R
13 14 15
29 30 31
URP3 UWP3
— — —
R R R
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