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12.5.1 Decrementer Register
The 32-bit decrementer (DEC) register is a special-purpose register defined by PowerPC
architecture. The decrementer causes an interrupt whenever Bit 0 changes from a logic 0 to
a logic 1. The contents of this register can be read or written to by the mfspr or mtspr
instruction. This register is undefined at reset. The decrementer is powered by standby
power and continues counting when standby power is applied. To enable the decrementer
control bits, use the timebase control and status register. The decrementer and timebase
share the same TMBCLK.
DEC
BIT
0
1
2
FIELD
RESET
R/W
SPR
BIT
16
17
18
FIELD
RESET
R/W
SPR
NOTE: — = Undefined.
DEC—Decrementer
This field is used by a down counter to cause decrementer interrupts. A read of this register
always returns the current count value from the down counter.
MOTOROLA
3
4
5
6
7
DEC
—
R/W
22
19
20
21
22
23
DEC
—
R/W
22
MPC823e REFERENCE MANUAL
System Interface Unit
8
9
10
11
12
24
25
26
27
28
13
14
15
29
30
31
12-13
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