Mmu Tablewalk Base Register - Motorola MPC823e Reference Manual

Memory Management Unit
11.6.1.12 MMU TABLEWALK BASE REGISTER. The MMU tablewalk base (M_TWB)
register contains a pointer to the level one table to be used in hardware-assisted tablewalk
mode.
M_TWB
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD L1TB
RESET —
R/W R/W
ADDR
NOTE: — = Undefined.
L1TB—Tablewalk Level 1 Base Value
These bits are the most-significant bits of the level one pointer.
L1INDX—Level 1 Table Index
This field is ignored on write. It returns MD_EPN[0:9] on read when MD_CTR
MD_EPN[2:11] when MD_CTR
Bits 30–31—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
11-36
3 4 5 6 7
L1TB
—
R/W
SPR 796
19 20 21 22 23
SPR 796
= 0.
TWAM
MPC823e REFERENCE MANUAL
8 9 10 11 12
24 25 26 27 28
L1INDX
—
R/W
13 14 15
29 30 31
RESERVED
0
R/W
= 1 and
TWAM
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