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G0H—General-Purpose Line 0 Higher
This field defines the state of the GPL0 signal during clock phase 4.
10 = The GPL0 signal is asserted at the trailing edge of GCLK1.
11 = The GPL0 signal is negated at the trailing edge of GCLK1.
00 = The GPL0 signal is driven at the trailing edge of GCLK1 as defined in the G0CLx
field of the MxMR.
G1T4—General-Purpose Line 1 Timing 4
This bit defines the state of the GPL1 signal during clock phases 1 through 3.
0 = The GPL1 signal is asserted at the trailing edge of GCLK2.
1 = The GPL1 signal is negated at the trailing edge of GCLK2.
G1T3—General-Purpose Line 1 Timing 3
This bit defines the state of the GPL1 signal during clock phase 4.
0 = The GPL1 signal is asserted at the trailing edge of GCLK1.
1 = The GPL1 signal is negated at the trailing edge of GCLK1.
G2T4— General-Purpose Line 2 Timing 4
This bit defines the state of the GPL2 signal during clock phases 1 through 3.
0 = The GPL2 signal is asserted at the trailing edge of GCLK2.
1 = The GPL2 signal is negated at the trailing edge of GCLK2.
G2T3—General-Purpose Line 2 Timing 3
This bit defines the state of the GPL2 signal during clock phase 4
0 = The GPL2 signal is asserted at the trailing edge of GCLK1.
1 = The GPL2 signal is negated at the trailing edge of GCLK1.
G3T4—General-Purpose Line 3 Timing 4
This bit defines the state of the GPL3 signal during clock phases 1 through 3.
0 = The GPL3 signal is asserted at the trailing edge of GCLK2.
1 = The GPL3 signal is negated at the trailing edge of GCLK2.
G3T3—General-Purpose Line 3 Timing 3
This bit defines the state of the GPL3 signal during clock phase 4.
0 = The GPL3 signal is asserted at the trailing edge of GCLK1.
1 = The GPL3 signal is negated at the trailing edge of GCLK1.
MOTOROLA
MPC823e REFERENCE MANUAL
Memory Controller
15-51
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