Basic Instruction Pipeline; Sequencer Unit - Motorola MPC823e Reference Manual

The PowerPC Core

6.2.2 Basic Instruction Pipeline

Figure 6-3 illustrates the basic instruction pipeline timing.
FETCH
DECODE
READ + EXECUTE
WRITE BACK
L ADDRESS DRIVE
L DATA
LOAD WRITE BACK
BRANCH DECODE
BRANCH EXECUTE
Figure 6-3. Basic Instruction Pipeline Timing Diagram

6.3 SEQUENCER UNIT

The instruction sequencer is the heart of the core. It controls data flow among execution
units and register files, implements the basic instruction pipeline, fetches instructions from
the memory system and issues them to available execution units, and maintains a state
history so it can back up the machine in the event of an exception. The sequencer data path
is illustrated in Figure 6-4. In addition, the sequencer implements all branch processor
instructions, including flow control and condition register instructions.
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