Mmu Instruction Tablewalk Control Register - Motorola MPC823e Reference Manual

11.6.1.10 MMU INSTRUCTION TABLEWALK CONTROL REGISTER. The MMU
instruction tablewalk control (MI_TWC) register contains the access protection group and
page size of the entry to be loaded into the translation lookaside buffer.
MI_TWC
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD RESERVED
RESET
R/W
ADDR
NOTE: — = Undefined.
Bits 0–22 and 30—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
APG—Access Protection Group
A maximum of 16 protection groups are supported. The default value of instruction TLB miss
is 0.
G—Guarded Storage Attribute for Entry
Default value on instruction TLB miss is 0.
0 = Unguarded storage.
1 = Guarded storage.
PS—Page Size Level One
Default value on instruction TLB miss is 00.
00 = Small (4K or 16K).
01 = 512K.
11 = 8M.
10 = Reserved.
MOTOROLA
3 4 5 6 7
RESERVED
0
R/W
SPR 789
19 20 21 22 23
0
R/W
SPR 789
MPC823e REFERENCE MANUAL
Memory Management Unit
8 9 10 11 12
24 25 26 27 28
APG G PS
— — —
R/W R/W R/W
13 14 15
29 30 31
RES V
0 —
R/W R/W
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