Motorola MPC823e Reference Manual page 400

Memory Controller
15.5.1.1 INTERNAL/EXTERNAL MEMORY ACCESS REQUESTS. When any of the
internal masters request a new access to external memory, the address and type of the
transfer are compared to each one of the valid banks defined in the base register. The value
of the MS field in the base register selects the UPM that will handle the memory access. You
must ensure that the appropriate UPM entries are created prior to your request.
The external memory access requests consist of read single beat, read burst, write single
beat, and write burst. A single beat cycle is generated by the master to a cache-inhibited
memory bank. A typical burst cycle is generated to the memory that allows multiple
accesses. It only occurs when your memory is burstable. A single beat cycle starts out with
one transfer start and ends with one transfer acknowledge. For a 32-bit access, the burst
cycle starts out with one transfer start but ends with four transfer acknowledges. For a 16-bit
bus, there are eight transfer acknowledges. For an 8-bit bus, there are 16 transfer
acknowledges.
15.5.1.2 MEMORY PERIODIC TIMER REQUESTS. Each UPM contains a periodic timer
that can be programmed to generate periodic service requests that will be indexed into the
RAM array. Figure 15-22 illustrates the hardware associated with memory periodic timer
request generation. In general, the periodic timer is used for refresh cycle operation.
SYSTEM
BRG PRESCALER
CLOCK (IN THE SCCR)
Figure 15-22. Memory Periodic Timer Request Block Diagram
Note: The UPM refresh is done in a round robin manner. If more than one chip-select
uses the same UPM, the refreshes will progress through each one. For example,
if you have three chip-selects using UPMA, you would need to set the periodic
timer A period to one-third the normal refresh.
15-42
MEMORY
PERIODIC
TIMER
PRESCALER
(IN THE MPTPR)
MPC823e REFERENCE MANUAL
UPMA PERIODIC
PERIODIC
TIMER REQUEST
TIMER A
(PTA)
PERIODIC
UPMB PERIODIC
TIMER B
TIMER REQUEST
(PTB)
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