Motorola MPC823e Reference Manual page 461

Microprocessor for mobile computing
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18. SPI RX
19. SPI TX
2
20. I
C RX
2
21. I
C TX
22. RISC timer tables
23. IDMA DREQ1 (option 3)
24. IDMA DREQ2 (option 3)
16.2.4 Executing Microcode From RAM or ROM
The microcontroller can execute microcode from a portion of 8K dual-port RAM. Depending
on the size of your microcode, you can program the ERAM field in the RCCR to protect the
first 512 bytes, 1,024 bytes, or 2,048 bytes of on-chip RAM to allow the microcontroller
exclusive access. You can execute microcode from the dual-port RAM or on-chip ROM. This
flexibility not only allows Motorola to add more protocols or enhancements to the MPC823e,
but it also allows you to obtain binary microcode. Refer to Table 16-1 for more information.
16.2.5 RISC Configuration and Control Registers
The 32-bit RISC controller configuration register (RCCR) and RISC microcode development
support control (RMDS) register are used to configure and control the RISC microcontroller.
The RCCR configures the microcontroller to run microcode from ROM or RAM and controls
the RISC internal timer. The RMDS determines the regions of the dual-port RAM that can
contain executable microcode. It is recommended that you write to these two registers as if
they were a single 32-bit register.
The ERAM4K bit is cleared in the RMDS if the RCCR's location is accessed as either part
of a half-word or byte access. RMDS is used in conjunction with the ERAM field of the RCCR
to determine the valid address space for executable microcode. If the ERAM4K bit is to be
set, the RMDS register must be accessed as part of a word starting at IMMR+0x9C4 to
IMMR+0x9C7.
RCCR-RMDS
BIT
0
1
2
FIELD
TIME
RES
RESET
0
0
R/W
R/W
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
MOTOROLA
3
4
5
6
7
TIMEP
0
R/W
(IMMR & 0xFFFF0000) + 0x9c4
19
20
21
22
23
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x9c6
MPC823e REFERENCE MANUAL
Communication Processor Module
8
9
10
11
DR2M
DR1M
DRQP
0
0
0
R/W
R/W
R/W
24
25
26
27
ERAM4K
RESERVED
0
R/W
12
13
14
15
EIE
SCD
ERAM
0
0
0
R/W
R/W
R/W
28
29
30
31
0
R/W
16-7

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