Motorola MPC823e Reference Manual page 538

Communication Processor Module
16.5.1 SDMA Bus Arbitration and Transfers
The instruction cache, data cache, system interface unit, and SDMA can become internal
bus masters whose relative priority can be determined by examining their arbitration IDs.
However, you can only adjust SDMA arbitration. All other arbitration IDs are fixed. All 12
SDMA channels share the same ID that you are responsible for programming. Any SDMA
channel can arbitrate for the bus against the other existing internal or external masters.
Once an SDMA channel obtains the system bus, it remains the bus master for one
transaction (a byte, half-word, word, or burst) before relinquishing the bus. This feature, in
combination with the zero clock arbitration overhead provided by the U-Bus is beneficial to
bus efficiency and low bus latency.
With character-oriented protocols, the SDMA writes characters to memory without waiting
for multiple characters to be received first and it always reads words. This is consistent with
the need to provide low-latency operation on character-oriented protocols that are used at
slower rates. The read or write operation may take multiple bus cycles if the memory
provides a less than 32-bit port size. For instance, a 32-bit word read from a 16-bit memory
takes two SDMA bus cycles. The entire operand (4-word burst, 32 bits on reads, and 8, 16,
or 32 bits on writes) will be transferred in back-to-back bus cycles before the SDMA
relinquishes the bus. The SDMA can steal cycles with no arbitration overhead when the
MPC823e is bus master.
OTHER CYCLE
CLK
TS
TA
SDMA INTERNALLY
REQUESTS THE BUS
16-84
SDMA CYCLE
Figure 16-37. SDMA Bus Arbitration
MPC823e REFERENCE MANUAL
OTHER CYCLE
MOTOROLA