Motorola MPC823e Reference Manual page 460

Communication Processor Module
16.2.2 Communication Between the Microcontroller and Core
The RISC microcontroller communicates with the core in the following ways:
• By exchanging parameters using the 8K dual-port RAM. With simultaneous accesses,
the microcontroller experiences a one-clock delay when accessing the dual-port RAM,
but the host is never delayed.
• By executing special commands that are issued by the host via the CPM command
register (CPCR). These commands must only be issued in special situations like
exceptions or error recovery.
• By generating interrupts using the CPM interrupt controller.
• By allowing the core to configure the CPM via the RISC controller configuration register
• By allowing the core to read the CPM status and event registers at any time.
The core communicates with the CPM by configuring the RCCR.
16.2.3 Communication Between the Microcontroller and Peripherals
The RISC microcontroller uses the peripheral bus to communicate with all of its peripherals.
The serial communication controllers (SCCs) and universal serial bus (USB) have separate
receive and transmit FIFOs. The SCC2 FIFOs are 32 bytes and the SCC3 and USB FIFOs
are 16 bytes each. However, the serial management controller, serial peripheral interface,
2
and I C FIFO sizes are all double-buffered. The following prioritized list contains the
processing order of the microcontroller from highest to lowest priority.
1. Reset in CPM command register or at reset
2. SDMA bus error
3. Commands issued to the command register, including DSP-related commands
4. IDMA DREQ1 (default setting)
5. IDMA DREQ2 (default setting)
6. USB Reception (RX)
7. USB Transmission (TX)
8. SCC2 RX
9. SCC2 TX
10. SCC3 RX
11. SCC3 TX
12. IDMA DREQ1 (option 2)
13. IDMA DREQ2 (option 2)
14. SMC1 RX
15. SMC1 TX
16. SMC2 RX
17. SMC2 TX
16-6 MPC823e REFERENCE MANUAL MOTOROLA