Motorola MPC823e Reference Manual page 134

INSTRUCTION CACHE / INSTRUCTION MMU INTERFACE
NEXT ADDRESS
GENERATION
CONTROL BUS
WRITEBACK BUS
(2 SLOTS / CLOCK)
CONTR
REGS
SOURCE BUSES
(4 SLOTS / CLOCK)
HISTORY BUFFER
INSTRUCTION QUEUE
Figure 6-2. Instruction Flow Conceptual Diagram
MOTOROLA
SEQUENCER
BRANCH
UNIT
GPR GPR
(32 X 32) HISTORY
Figure 6-1. Block Diagram of the Core
RETIRE
ISSUE
FETCH
MPC823e REFERENCE MANUAL
DATA CACHE / DATA MMU INTERFACE
CORE
INSTRUCTION
QUEUE
IMUL / ALU / LDST
IDIV BFU ADDR
EXECUTION UNITS
WRITEBACK
BRANCH
UNIT
The PowerPC Core
LDST
FIX
DATA
6-3