Motorola MPC823e Reference Manual page 378

Memory Controller
PTAE—Periodic Timer A Enable
This bit allows the periodic timer A to request service.
0 = Periodic timer A is disabled.
1 = Periodic timer A is enabled.
AMA—Address Multiplex Size A
This field specifies the number of address lines to be output on the bus at the first clock of
the memory cycle (see Table 15-7 on page 15-60 for more information). The AMX field of
the RAM array entry controls the output of the address lines, as shown in Table 15-3
(page 15-37). For example, these address lines can be used to connect to the DRAM
devices that require row and columns to be multiplexed on the same pin.
Bits 12 and 15—Reserved
These bits are reserved and must be set to 0.
DSA—Disable Timer Period
This bit guarantees a minimum time between accesses to the same memory bank if it is
controlled by the UPMA. The TODT bit turns on the disable timer in the RAM array and,
when expired, the UPMA allows the machine access to issue a memory pattern to the same
memory region. Accesses to different memory regions using two or more chip-selects can
be handled by this same UPMA, assuming they have the same timing. The maximum
disable period is four clock cycles. When switching to a different bank that requires more
than four clock cycles, you must add more UPM RAM word to meet your time requirement.
Refer to Section 15.5.4.2 RAM Word Operation for more specific DRAM example
information.
00 = 1-cycle disable period.
01 = 2-cycle disable period.
10 = 3-cycle disable period.
11 = 4-cycle disable period.
G0CLA—General Line 0 Control A
This field selects the address line that is output to the internal GPL0 signal when the UPMA
is selected to control memory access. It can be used for precharge control on SDRAMs.
000 = A12 is selected.
001 = A11 is selected.
010 = A10 is selected.
011 = A9 is selected.
100 = A8 is selected.
101 = A7 is selected.
110 = A6 is selected.
111 = A5 is selected.
15-20 MPC823e REFERENCE MANUAL MOTOROLA