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16.9.18.5 SCCx APPLETALK PROGRAMMING EXAMPLE. Except for the previously
discussed register programming, use the example in Section 16.9.16.14 SCC2 HDLC
Programming Example #1 .
16.9.19 The SCCx in Asynchronous HDLC Mode
Asynchronous HDLC is a frame-based protocol that uses HDLC framing techniques in
conjunction with UART-type characters. This protocol is typically used as the physical layer
for the point-to-point protocol (PPP) and the infrared link access protocol (IRLAP). Even
though asynchronous HDLC can be implemented in conjunction with the core, it is more
efficient and less computationally intensive to allow the communication processor module
to perform the framing and transparency functions. A serial communication controller in
ASYNC HDLC mode is also referred to as a SCCx ASYNC HDLC controller.
16.9.19.1 FEATURES. The following list summarizes the main features of the SCCx in
asynchronous HDLC mode:
• Flexible data buffer structure that allows an entire frame or a section of a frame to be
transmitted and received
• Separate interrupts for received frames and transmitted buffers
• Automatic CRC generation and checking
• Support for nonmultiplexed serial interface control signals
• Automatic generation of opening and closing flags
• Reception of frames with only one "shared" flag
• Automatic generation and stripping of transparency characters according to RFC 1549
using transmit and receive control character maps
• Programmable opening flag, closing flag, and control escape characters
• Automatic transmission of the abort sequence after the STOP TRANSMIT command is
issued
• Automatic transmission of idle characters between frames
16.9.19.2 SCCx ASYNC HDLC CHANNEL FRAME TRANSMISSION PROCESS. The
SCCx ASYNC HDLC controller, is designed to operate with a minimum amount of
intervention from the core and operates similar to the SCCx in HDLC mode. When the core
enables the transmitter and sets the R bit in the first transmit buffer descriptor, the SCCx
ASYNC HDLC controller fetches the data from memory and starts transmitting the frame.
When the controller reaches the end of the current buffer descriptor, the CRC and closing
flag are appended if the L bit in the TX buffer descriptor is set. If the CM bit is clear, the
asynchronous HDLC transmitter writes the frame status bits into the buffer descriptor and
clears the R bit. If the I bit is set, the controller sets the TXB bit in the SCCE–ASYNC HDLC
register. Thus, the I bit can be used to generate an interrupt after each buffer, after a group
of buffers, or after each complete frame has been transmitted.
MOTOROLA
MPC823e REFERENCE MANUAL
Communication Processor Module
16-269
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