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Memory Management Unit
11.2 ADDRESS TRANSLATION
The MPC823e core generates 32-bit effective addresses and, when enabled, the memory
management unit translates the effective address to a real address that is used for cache or
memory access. If disabled, the effective address is passed as the real address to the
memory, which bypasses the appropriate translation lookaside buffer. When the memory
management unit is enabled, the effective address is used to locate a TLB entry if found or
hit, which will then provide the real address mapping and storage attributes. For
performance reasons, a translation lookaside buffer is implemented in each hardware cache
to hold recently used address translations. In the MPC823e, the table lookup and TLB reload
are performed by a software routine with little hardware assistance. This partition simplifies
the hardware and gives the system the opportunity to choose the translation table structure.
A TLB hit in multiple entries is avoided during the TLB reload phase. The TLB logic
recognizes that the effective page number (EPN) currently loaded into the translation
lookaside buffer overlaps another EPN. At least when taking into account the page sizes,
subpage validity flags, problem/privileged state, address space ID (ASID), and the SH
values of the TLB entries. When such an event occurs, the current EPN is written into the
translation lookaside buffer and the entry of the other EPN is invalidated from the translation
lookaside buffer.
The memory management unit supports a multiple virtual address space model and, when
enabled, each translation is associated with an ASID. In this case, for the translation to be
valid, its ASID must be equal to the current address space ID (CASID) that is in effect when
an access is performed.
11.2.1 Translation Lookaside Buffer Operation
Two translation lookaside buffers are provided in the MPC823e—one for instruction fetches
and one for data accesses. The translation lookaside buffer contains pointers to pages in
the real memory where data is indexed by the effective page number and it can hold entries
with different page sizes. The entry page size controls the number of effective address bits
to be compared and the number of least-significant effective address bits that remain
untranslated and passes them as least-significant real address bits.
For a 4K page size, four subpage validity flags are supported, thus allowing any combination
of 1K subpages to be mapped. For any other page size, all of these flags must have the
same value. Programming pages other than 4K pages with different valid bits is considered
a programming error. The subpage validity flags can be manipulated to implement effective
page sizes of 1K, 2K, 3K, 4K, or any other combination of 1K subpages. However, subpages
of an effective page frame must all map to the same real page. During the translation
process, the effective address, the processor problem state (MSR
), and CASID are
PR
provided to the translation lookaside buffer. See Figure 11-1 for details. In the translation
lookaside buffer, the effective address and CASID are compared with the EPN and ASID of
each entry. The CASID is only compared when the matching entry was programmed as
nonshared. See Section 11.6.1.6 MMU Instruction Real Page Number Register and
Section 11.6.1.7 MMU Data Real Page Number Register for details.
11-2
MPC823e REFERENCE MANUAL
MOTOROLA
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