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Communication Processor Module
Note: The USB or SCCx CISR bit positions are not affected by the relative priority
between the USB or SCCs. If the error vector is taken, no bit in the CISR is set.
All undefined bits in the CISR return zeros when read. You can control the extent
to which CPM interrupts can interrupt other CPM interrupts by selectively clearing
the CISR. A new interrupt is processed if it has a higher priority than the higher
priority interrupt having its CISR bit set. Thus, if an interrupt routine sets the
interrupt mask bit in the core and also clears its CISR bit at the beginning of the
interrupt routine, a lower priority interrupt can interrupt the higher one, as long as
the lower priority interrupt is of higher priority than any other CISR bits that are
currently set.
16.15.5.5 CPM INTERRUPT VECTOR REGISTER. The CPM interrupt vector register
(CIVR) is a 16-bit register. Bits 0-4 of the register contain the interrupt vector number. To
update the register with the current interrupt vector number, the core must set the IACK bit.
The bit is cleared after one clock cycle. The register can be read at any time.
CIVR
BIT
0
1
2
FIELD
VECTOR NUMBER
RESET
0
R/W
R/W
ADDR
16.15.6 Interrupt Handling Examples
You can use the following examples to learn how to properly handle CPM interrupts.
16.15.6.1 PC6 INTERRUPT HANDLER EXAMPLE. In this example, the CPM interrupt
controller hardware clears the PC6 bit in the CIPR during the interrupt acknowledge cycle.
Use the following steps to handle an interrupt source without multiple events.
1. Set the IACK bit in the CIVR.
2. Read the vector to access the interrupt handler.
3. Handle the event associated with a change in the state of the PC6 pin.
4. Clear the PC6 bit in the CISR.
5. Execute the rfi instruction.
16-511
3
4
5
6
7
(IMMR & 0xFFFF0000) + 0x930
MPC823e REFERENCE MANUAL
8
9
10
11
12
RESERVED
0
R/W
13
14
15
IACK
0
R/W
MOTOROLA
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