Motorola MPC823e Reference Manual page 922

Microprocessor for mobile computing
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Communication Processor Module
16.13.7 Programming the I
2
16.13.7.1 I
C MODE REGISTER. The read/write I
2
the I
C operation mode and clock source.
I2MOD
BIT
0
1
FIELD
RESERVED
RESET
0
R/W
R/W
ADDR
Bits 0–1—Reserved
These bits are reserved and must be set to 0.
REVD—Reverse Data
This bit determines the receive and transmit character bit order.
0 = Normal operation. Most-significant bit of character transmitted and received first.
1 = Reverse data. Least-significant bit of character transmitted and received first.
GCD—General Call Disable
This bit determines if the receiver will acknowledge a general call address.
0 = General call address is enabled.
1 = General call address is disabled.
FLT—Clock Filter
This bit determines if the I
0 = I2CLK is not filtered.
1 = I2CLK is filtered by a digital filter.
PDIV—Pre Divider
This field determines the division factor of the clock before it is fed into the baud rate
generator. The clock source for the I
system interface unit.
00 = Use the BRGCLK/32 as the input to the I
01 = Use the BRGCLK/16 as the input to the I
10 = Use the BRGCLK/8 as the input to the I
11 = Use the BRGCLK/4 as the input to the I
16-468
2
C Controller
2
3
REVD
GCD
0
0
R/W
R/W
(IMMR & 0xFFFF0000) + 0x860
2
C input clock is filtered to prevent spikes in a noisy environment.
2
C controller is the BRGCLK that is generated by the
2
2
MPC823e REFERENCE MANUAL
2
C mode (I2MOD) register controls both
4
5
6
FLT
PDIV
0
0
R/W
R/W
2
C baud rate generator.
2
C baud rate generator.
C baud rate generator.
C baud rate generator.
7
EN
0
R/W
MOTOROLA

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