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The PowerPC Core
6.6.9 Instruction Timing
The following table summarizes the different load/store instructions timing in the case of
zero wait state memory references on a parked bus. With external memory accesses,
pipelined external accesses are assumed.
INSTRUCTION TYPE
Fixed-Point Single Target
Register Load (Aligned)
Fixed-Point Single Target
Register Store (Aligned)
Load/Store Multiple
NOTE: N denotes the number of registers transferred.
String instructions are broken into a series of aligned bus accesses. Figure 6-8 illustrates
the maximum number of bus cycles needed for string instruction execution.
00'h
04'h
08'h
0C'h
10'h
14'h
18'h
Figure 6-8. Number of Bus Cycles Needed For String Instruction Execution
6.6.10 Stalling Storage Control Instructions
A storage control instruction waits one clock before it is taken.
6.6.11 Accessing Off-Core Special Registers
Access to special registers—mtspr and mfspr—implemented off-core is executed by the
load/store unit via the internal bus using a special cycle. Refer to Section 6.4.1.1 Physical
Location of Special Registers for detailed information. If the access terminates in a bus
error, then an implementation-dependent software emulation interrupt is taken. All write
operations to off-core special registers (mtspr) are previously synchronized. In other words,
the instruction is not taken until all prior instructions terminate.
6-30
Table 6-12. Load/Store Instructions Timing
LATENCY
DATA CACHE
2 Clocks
1 Clock
1 + N
00
01
02
04
05
06
08
09
0A
0C
0D
0E
10
11
12
14
15
16
18
19
1A
MPC823e REFERENCE MANUAL
CLEARED FROM
LOAD/STORE UNIT
EXTERNAL
DATA
MEMORY
CACHE
5 Clocks
2 Clocks
1 Clock
2 Clocks
1 + N
N 1
+
3 N
+
+
--------------
3
03
07
2 BUS CYCLES
0B
WORD
TRANSFERS
0F
3 BUS CYCLES
13
17
2 BUS CYCLES
1B
EXTERNAL
MEMORY
5 Clocks
5 Clocks
N 1
+
3 N
+
+
--------------
3
MOTOROLA
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