Motorola MPC823e Reference Manual page 685

7. Write to RBASE and TBASE in the SCC2 parameter RAM to point to the RX and TX
buffer descriptors in the dual-port RAM. Assuming one RX buffer descriptor at the
beginning of dual-port RAM and one TX buffer descriptor following that RX buffer
descriptor, write 0x2000 to RBASE and 0x2008 to TBASE.
8. Write 0x0041 to the CPCR to execute the INIT RX AND TX PARAMS command for
SCC2.
9. Write 0x15 to the RFCR and 0x15 to the TFCR for normal operation.
10. Write the maximum number of bytes per receive buffer to the MRBLR. For this case,
assume 16 bytes, so MRBLR = 0x0010.
11. Write 0x0000 to the MAX_IDL in the SCC2 UART parameter RAM to disable the
MAX_IDL functionality for this example.
12. Write 0x0001 to the BRKCR, so that if a STOP TRANSMIT command is issued, one
break character is sent.
13. Clear PAREC, FRMEC, NOSEC, and BRKEC in the SCC2 UART parameter RAM.
14. Clear UADDR1 and UADDR2. They are not used.
15. Clear TOSEQ. It is not used.
16. Write 0x8000 to CHARACTER1–CHARACTER8. They are not used.
17. Write 0xC0FF to the RCCM. It is not used.
18. Initialize the RX buffer descriptor. Assume the RX data buffer is at 0x00001000 in main
memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (optional), and
0x00001000 to RX_BD_Pointer.
19. Initialize the TX buffer descriptor. Assume the TX data buffer is at 0x00002000 in main
memory and contains five 8-bit characters. Write 0xB000 to TX_BD_Status, 0x0010
to TX_BD_Length, and 0x00002000 to TX_BD_Pointer.
20. Write 0xFFFF to the SCCE–UART register to clear any previous events.
21. Write 0x0003 to the SCCM–UART register to enable the transmit and receive
interrupts.
22. Write 0x20000000 to the CIMR so the SCC2 can generate a system interrupt. The
CICR must also be initialized.
23. Write 0x00000020 to the GSMR_H to configure a small receive FIFO width.
24. Write 0x00028004 to the GSMR_L to configure 16× oversampling for transmit and
receive, the CTS2 and CD2 pins to automatically control transmission and reception
(DIAG field) and the SCC2 UART mode. Notice that the transmitter (ENT bit) and
receiver (ENR bit) have not been enabled yet.
25. Write 0xB000 to the PSMR–SCC2 UART to configure automatic flow control using the
CTS2 pin, 8-bit characters, no parity, 1 stop bit, and asynchronous SCC2 UART
operation.
26. Write 0x00028034 to the GSMR_L register to enable the SCC2 transmitter and
receiver. This additional write ensures that the ENT and ENR bits are enabled last.
MOTOROLA MPC823e REFERENCE MANUAL
Communication Processor Module
16-231