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Instruction Cache
9.3.2 Instruction Cache Miss
When an instruction cache miss occurs, the address of the missed instruction is driven on
the internal bus with a 4-word burst transfer read request. A cache line is then selected to
receive the data that will be coming from the bus. The selection algorithm gives first priority
to invalid lines. If none of the lines in the selected set are invalid, then the least recently used
line is selected for replacement. Locked lines are never replaced. The transfer begins with
the word requested by the instruction unit, followed by the remaining words of the line, then
by the word at the beginning of the lines.
When the missed instruction is received from the bus, it is immediately delivered to the
instruction unit and also written to the burst buffer. As subsequent instructions are received
from the bus, they are written into the burst buffer and delivered to the instruction unit either
directly from the bus or from the burst buffer. When the line resides in the burst buffer, it is
written to the cache array as long as it is not busy with an instruction unit request. If a bus
error is encountered on the access to the requested instruction, then a machine check
interrupt is taken. If a bus error occurs on any access to other words in the line, then the
burst buffer is marked invalid and the line is not written to the array. However, if no bus error
is encountered, the burst buffer is marked valid and eventually written to the array.
If you receive a cache-inhibit signal, the line is only written to the burst buffer and not to the
cache. Instructions that are stored in the burst buffer and originate in a cache-inhibited
memory region are only used once before they are refetched. Refer to
Section 9.4.6 Instruction Cache Read for more information.
9.3.3 Instruction Fetch On A Predicted Path
The core allows branch prediction so branches can issue as early as possible. This
mechanism allows instruction prefetch to continue while an unresolved branch is being
computed and the condition is being evaluated. Instructions fetched after unresolved
branches are considered fetched on a predicted path. These instructions may be discarded
later if it turns out that the machine has followed the wrong path. To minimize power
consumption, the MPC823e instruction cache does not initiate a miss sequence in most
cases when the instruction is inside a predicted path. The MPC823e instruction cache
evaluates fetch requests to see if they are inside a predicted path and if a hit is detected, the
requested data is delivered to the core. However, if a cache miss is detected, the miss
sequence is usually not initiated until the core finishes branch evaluation.
9.4 INSTRUCTION CACHE COMMANDS
The MPC823e instruction cache supports the PowerPC invalidate instruction with some
additional commands that help control the cache and debug the information stored in it. The
additional commands are implemented using the three special-purpose control registers
mentioned previously in Section 9.2 Programming the Instruction Cache . Most of the
commands are executed immediately after the control register is written and unable to
generate any errors. Therefore, when executing these command, there is no need to check
the error status in the IC_CST.
9-8
MPC823e REFERENCE MANUAL
MOTOROLA
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