Programming The Instruction Cache - Motorola MPC823e Reference Manual

Instruction Cache
DATA
32
BYPASS
MUX
2->1
INSTRUCTION
TO CORE
Figure 9-2. Cache Data Path Block Diagram

9.2 PROGRAMMING THE INSTRUCTION CACHE

Three special-purpose registers can be used to control the instruction cache with the mfspr
and mtspr instructions:
• Instruction cache control and status register (IC_CST)
• Instruction cache address register (IC_ADR)
• Instruction cache data port register (read-only) (IC_DAT)
These registers are privileged and any attempt to access them while the core is in the
problem state (MSR =1) results in a program interrupt.
PR
9-4
ADDRESS [20:27]
SET
DECODER
ADDRESS [28:29]
STREAM
WORD
128
32
HIT
SELECT
MUX
MUX
2->1
4->1
MPC823e REFERENCE MANUAL
16K
CACHE
ARRAY
128
4
128
WORDS
LINE
128
BUFFER
4
WORDS
BURST
BUFFER
128
32
INTERNAL BUS DATA
MOTOROLA