Communication Processor Module
RXDx
D
HSRCLK
CK
Figure 16-70. DPLL Receiver Block Diagram
TENC
TDCR
TEND
HSTCLK
SCCT DATA
TINV
Figure 16-71. DPLL Transmitter Block Diagram
16-194
RENC
RDCR
EDGE
DPLL
TSNC
RECEIVER
RINV
RXDx
HSRCLK
RINV
RENC π NRZI
Q
DPLL
TRANSMITTER
ENCODED
DATA
0
0
1
1
S
S
X1 MODE
TENC = NRZI
MPC823e REFERENCE MANUAL
0
HSRCLK
1
CARRIER SNC
S
NOISE
HUNTING
X1 MODE
DECODED DATA
0
SCCRDATA
1
S
X1 MODE
0
HSTCLK
1
S
X1 MODE
D
Q
HSTCLK
CK
D
Q
HSTCLK
CK
RCLK
TCLK
TXEN
TXDx
MOTOROLA