Motorola MPC823e Reference Manual page 366

Memory Controller
The memory controller registers are used by the general-purpose chip-select machine and
the user-programmable machines as specified in Table 15-1. See Section 15.3.1 Register
Descriptions for specific register information.
Table 15-1. Memory Controller Register Usage
REGISTER
Base Register Bank 0-7 Register (BRx)
Option Register Bank 0-7 Register (ORx)
Memory Status Register (MSTAT)
Memory Command Register (MCR)
Machine A Mode Register (MAMR)
Machine B Mode Register (MBMR)
Memory Data Register (MDR)
Memory Address Register (MAR)
Memory Periodic Timer Prescaler Register (MPTPR)
The memory controller supports multiple port sizes. Predefined 8-bit ports can be accessed
as odd or even bytes, predefined 16-bit ports can be accessed as odd or even bytes and
even half-words on data bus bits 0 through 15. Predefined 32-bit ports can be accessed as
odd bytes, even bytes, odd half-words, even half-words, or words on word boundaries. The
port size is specified by the PS field in the base register.
The WP bit of the base register restricts write accesses to a certain address range. If you try
to write in this area, a write-protect violation occurs and the WPER bit in the memory status
register is set.
Each time an internal or external bus cycle access is requested, the address and its
corresponding address type are compared to each one of the banks. If a match is found on
one of the memory controller banks, the attributes defined for that bank in the base and
option registers are used to control the memory access. However, if multiple matches are
found, the lowest numbered matched bank handles the memory access. It must be noted
that when external masters access memory controller-managed slaves on the bus, the
internal AT signals to the memory controller are forced to '100'.
Parity can be configured for any bank. It is generated and checked on a per-byte basis using
the DP[0:3] signals for the bank if the PARE bit is set in the base register. The OPAR bit in
the SIUMCR (described in Section 12.12.1.1 SIU Module Configuration Register)
determines the type of parity. Any parity error causes the associated PER bit in the memory
status register to be set. It also asserts the TEA signal and sets the corresponding DPB bit
in the TESR, which is described in Section 12.12.1.4 Transfer Error Status Register. The
memory controller asserts an internal transfer error signal when a parity error occurs (if
enabled).
15-8
USED BY THE GPCM
MPC823e REFERENCE MANUAL
USED BY A UPM
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