Motorola MPC823e Reference Manual page 463

SCD—Scheduler Configuration
Configure this bit as instructed in the download process of a Motorola-supplied RAM
microcode package.
0 = Normal operation.
1 = Alternate configuration of the scheduler.
ERAM—Enable RAM Microcode
Configure this field as instructed in the download process of a Motorola-supplied RAM
microcode package. This field is used in conjunction with the ERAM 4K bit to configure the
RAM microcode space.
ERAM (RCCR)
ERAM4K—Enable RAM Microcode (4K)
0 = Microcode is only executed from the first 2,048 bytes of the dual-port RAM.
1= Microcode is executed from the 2,048 bytes of the second half of the dual-port
RAM with a 512-byte extension.
16.2.6 RISC Microcontroller Commands
To initialize the serial channel or DMA, you can issue a command to the CPM command
register. The command you issue will ask the communication processor module to perform
further device-specific functions based on the information in the device's parameter RAM.
16.2.6.1 CPM COMMAND REGISTER. The core sets the FLG bit in the 16-bit,
memory-mapped, read/write CPM command register (CPCR) when it issues a command
and the communication processor module clears the FLG bit when the command is
completed. The core is now ready for the next command. Subsequent commands to the
CPCR can only be given when the FLG bit is clear. When issuing the software reset
command, the core must also set the FLG bit.
MOTOROLA
Table 16-1. RAM Microcode Configurations
BIT 0 IN
RMDS
01 0
10 0
11 0
01 1
10 1
11 1
MPC823e REFERENCE MANUAL
Communication Processor Module
MICROCODE ADDRESSES
2000-21ff and 2f00-2fff
2000-23ff and 2f00-2fff
2000-27ff and 2e00-2fff
2000-21ff, 2f00-2fff, 3000-37ff,
and 3a00-3bff
2000-23ff, 2f00-2fff, 3000-37ff,
and 3a00-3bff
2000-27ff, 2e00-2fff,
3000-37ff, and 3a00-3bff
16-9