Motorola MPC823e Reference Manual page 930

Communication Processor Module
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16.13.7.8 I C MASK REGISTER. The 8-bit read/write I
same bit formats as the I2CER. If a bit in the I2CMR is 1, the corresponding interrupt in the
I2CER is enabled. If the bit is zero, the corresponding interrupt in the I2CER is masked. This
register is cleared by reset.
I2CMR
BIT 0 1
FIELD RESERVED
RESET 0
R/W R/W
ADDR
16.13.8 I C Controller Initialization Sequence
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The following initialization sequence is for the I
read one byte from a slave device that contains an internal read address. The I
operates the SCL at 391kHz. A system frequency of 50MHz is assumed. The SDA and SCL
pins of the MPC823e are connected to an external 5V power supply with 6.8K Ohm to
10K Ohm resistors.
1. Configure the port B pins to enable the SDA and SCL pins. Write PBPAR, PBDIR, and
PBODR bits 26 and 27 with ones.
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2. Disable the I C controller by clearing the I2MOD register, including the EN bit. Now
you can modify other fields in the I2MOD register.
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3. Configure the I C dedicated baud rate generator to operate at 391kHz at a system
frequency of 50MHz by programming the divider and pre-divider. The overall I
rate generator clock divider is 128 (decimal) and is realized by establishing a
pre-divider of 8 and a divider of 16. Write the PDIV field of the I2MOD register with 2
to pre-divide by 8. Write the DIV field of the I2BRG register with 5 to divide by 16.
4. Write 0x0 to the I2CADD register to clear it.
5. Write 0x01 to the I2COM register to configure the I
operation.
6. Write 0x0001 to the SDCR to set the SDMA bus arbitration level to 5.
7. Write RBASE and TBASE in the I
descriptors in the dual-port RAM. Assuming the initial RX buffer descriptor at the
beginning of dual-port RAM and the initial TX buffer descriptor 64 bytes from the
beginning, write RBASE with 0x2000 and TBASE with 0x2040.
8. Write 0x11 into the CPCR to execute the INIT RX AND TX PARAMS command for I
9. Write 0x15 into the RFCR and TFCR for normal operation.
10. Write MRBLR with the maximum bytes per receive buffer. In this case, assume 16
bytes, so MRBLR = 0x10.
16-476
2 3 4
TXE RESERVED
0 0
R/W R/W
(IMMR & 0xFFFF0000) + 0x874
2
C controller to operate in master mode and
2
C parameter RAM to point to the RX and TX buffer
MPC823e REFERENCE MANUAL
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C mask register (I2CMR) has the
5 6
BSY TXB
0 0
R/W R/W
2
C controller
2
C controller for master mode
7
RXB
0
R/W
2
C baud
2
C.
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